Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or iii-v channel of semiconductor device

ABSTRACT

A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor.

FIELD OF THE INVENTION

The present disclosure relates generally to semiconductor devices, andmore particularly to forming gate structures in semiconductor devices.

BACKGROUND

Field effect transistors (FETs) are widely used in the electronicsindustry for switching, amplification, filtering and other tasks relatedto both analog and digital electrical signals. Most common among theseare metal oxide semiconductor field effect transistors (MOSFET or MOS),in which a gate structure is energized to create an electric field in anunderlying channel region of a semiconductor body, by which electronsare allowed to travel through the channel between a source region and adrain region of the semiconductor body. Continuing trends insemiconductor device manufacturing include a reduction in electricaldevice feature size (scaling), as well as improvements in deviceperformance in terms of device switching speed and power consumption.

SUMMARY

In one aspect of the present disclosure, a method of forming asemiconductor device is provided that includes forming a metal oxidematerial on a III-V channel region. Treating the metal oxide materialwith an oxidation process. The oxidation process is followed by thedeposition of a hafnium containing oxide. A gate conductor is formedatop the hafnium containing oxide, wherein source and drain regions areon opposing sides of the gate structure including the metal oxidematerial, the hafnium containing oxide and the gate conductor.

In another aspect of the present disclosure, a method of forming asemiconductor device is provided that includes forming an metal oxidematerial on a germanium containing semiconductor channel region; andtreating the metal oxide material with an oxidation process. The methodmay further include depositing of a hafnium containing oxide on themetal oxide material after the oxidation process, and forming a gateconductor atop the hafnium containing oxide. Source and drain regionsare on present on opposing sides of the gate structure including themetal oxide material, the hafnium containing oxide and the gateconductor.

In yet another aspect of the present disclosure, a semiconductor deviceis provided that may be formed on a germanium containing substrate andemploys a process for forming the gate structure of the semiconductordevice that includes a oxidation process. The semiconductor device mayinclude a channel region of a substrate including a germanium containingmaterial; and a gate structure including an interface dielectricmaterial comprising germanium, oxygen and nitrogen that is directly onthe substrate, a high-k dielectric layer comprising hafnium, aluminumand oxygen is present on the interface dielectric material, and a gateconductor is present atop the high-k dielectric layer. A source regionand a drain region are present on opposing sides of the channel region.

DESCRIPTION OF THE DRAWINGS

The following detailed description, given by way of example and notintended to limit the invention solely thereto, will best be appreciatedin conjunction with the accompanying drawings, wherein like referencenumerals denote like elements and parts, in which:

FIG. 1 is a flow chart illustrating one embodiment of a gate firstmethod for forming a semiconductor device on a III-V semiconductorsubstrate, in accordance with one embodiment of the present disclosure.

FIG. 2 is a side cross-sectional view depicting one embodiment offorming a metal oxide material on a III-V semiconductor channel regionor a germanium containing substrate, in accordance with the presentdisclosure.

FIG. 3 is a side cross-sectional view depicting treating the metal oxidematerial with an oxidation process, in accordance with one embodiment ofthe present disclosure.

FIG. 4 is a side cross-sectional view depicting depositing of a hafniumcontaining oxide on the metal oxide material after the oxidationprocess, in accordance with one embodiment of the present disclosure.

FIG. 5 is a side cross-sectional view depicting one embodiment offorming a material layer for a gate conductor on the hafnium containingoxide, in accordance with the present disclosure.

FIG. 6 is side cross-sectional view depicting one embodiment ofpatterning a gate structure.

FIG. 7 is a side cross-sectional view depicting forming source regionsand drain regions on opposing sides of the channel region, in accordancewith one embodiment of the present disclosure.

FIG. 8 is a plot of gate leakage for gate structures formed using oneembodiment of the method described with reference to FIGS. 1-7 incomparison to comparative examples that do not include an oxidationprocess as described in the present disclosure.

FIG. 9 is an electron energy loss spectroscopy (EELS) plot of thecomposition of an oxide region that is formed using the method describedwith reference to FIGS. 1-7.

FIG. 10 is a flow chart illustrating one embodiment of a gate lastmethod for forming a semiconductor device on a III-V semiconductorsubstrate, in accordance with one embodiment of the present disclosure.

FIG. 11 is a side cross-sectional view depicting forming a sacrificialgate structure on a III-V semiconductor substrate or germaniumcontaining substrate, forming source and drain regions on opposing sidesof a channel region of a semiconductor device, and forming a dielectriclayer having an upper surface that is coplanar with the sacrificial gatestructure.

FIG. 12 is a side cross-sectional view depicting removing thesacrificial gate structure to provide a gate opening to the channelregion of the semiconductor device, in accordance with one embodiment ofthe present disclosure.

FIG. 13 is a side cross-sectional view depicting one embodiment offorming a metal oxide material on a III-V semiconductor channel regionor a germanium containing substrate, in accordance with the presentdisclosure.

FIG. 14 is a side cross-sectional view depicting treating the metaloxide material with an oxidation process, in accordance with oneembodiment of the present disclosure.

FIG. 15 is a side cross-sectional view depicting depositing of a hafniumcontaining oxide on the metal oxide material after the oxidationprocess, in accordance with one embodiment of the present disclosure.

FIG. 16 is a side cross-sectional view depicting one embodiment offorming a material layer for a gate conductor on the hafnium containingoxide, in accordance with the present disclosure.

FIG. 17 is a flow chart illustrating one embodiment of a gate firstmethod for forming a semiconductor device on a germanium containingsubstrate, in accordance with one embodiment of the present disclosure.

FIG. 18 is a plot of Z-contrast scanning transmission electronmicroscope (Z-contrast STEM) measurements of an oxide region formed inaccordance with method illustrated in FIG. 17.

FIG. 19 is an electron energy loss spectroscopy (EELS) plot of thecomposition of an oxide region that is formed using the method describedwith reference to FIG. 17.

FIG. 20 an electron energy loss spectroscopy (EELS) plot of acomparative composition of an oxide region that is not formed using aprocess sequence using an oxidation step.

FIG. 21 is a plot illustrating the electrical impact of the oxidationtreatment applied to a bilayer of aluminum oxide and hafnium oxide, inaccordance with one embodiment of the present disclosure.

FIG. 22 is a plot illustrating the electrical impact of the optionalnitridation treatment applied to a bilayer of aluminum oxide and hafniumoxide, in accordance with one embodiment of the present disclosure.

FIG. 23 is a flow chart illustrating one embodiment of a gate lastmethod for forming a semiconductor device on a germanium containingsemiconductor substrate, in accordance with one embodiment of thepresent disclosure.

FIG. 24A is a top down view of a fin field effect transistor having agate structure formed in accordance with the present disclosure.

FIG. 24B is a side cross-sectional view along section line A-A of FIG.24A.

DETAILED DESCRIPTION

Detailed embodiments of the methods and structures of the presentdisclosure are described herein; however, it is to be understood thatthe disclosed embodiments are merely illustrative of the disclosedmethods and structures that may be embodied in various forms. Inaddition, each of the examples given in connection with the variousembodiments of the disclosure are intended to be illustrative, and notrestrictive. Further, the figures are not necessarily to scale, somefeatures may be exaggerated to show details of particular components.Therefore, specific structural and functional details disclosed hereinare not to be interpreted as limiting, but merely as a representativebasis for teaching one skilled in the art to variously employ themethods and structures of the present disclosure.

References in the specification to “one embodiment”, “an embodiment”,“an example embodiment”, etc., indicate that the embodiment describedmay include a particular feature, structure, or characteristic, butevery embodiment may not necessarily include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to affect such feature, structure, or characteristicin connection with other embodiments whether or not explicitlydescribed. For purposes of the description hereinafter, the terms“upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”,“bottom”, and derivatives thereof shall relate to the invention, as itis oriented in the drawing figures. The terms “overlying”, “atop”,“positioned on ” or “positioned atop” means that a first element, suchas a first structure, is present on a second element, such as a secondstructure, wherein intervening elements, such as an interface structure,e.g. interface layer, may be present between the first element and thesecond element. The term “direct contact” means that a first element,such as a first structure, and a second element, such as a secondstructure, are connected without any intermediary conducting, insulatingor semiconductor layers at the interface of the two elements.

The present disclosure is related to semiconductor devices, such asfield effect transistors. A “field effect transistor” is a transistor inwhich output current, i.e., source-drain current, is controlled by thevoltage applied to a gate structure. A field effect transistor typicallyhas three terminals, i.e., a gate structure, source region and drainregion. As used herein, the term “source” is a doped region in thesemiconductor device, in which majority carriers are flowing into thechannel. As used herein, the term “channel” is the region underlying thegate structure and between the source and drain of a semiconductordevice that becomes conductive when the semiconductor device is turnedon. As used herein, the term “drain” means a doped region insemiconductor device located at the end of the channel, in whichcarriers are flowing out of the transistor through the drain. A “gatestructure” means a structure used to control output current (i.e., flowof carriers in the channel) of a semiconducting device throughelectrical or magnetic fields. The gate structure typically includes atleast one gate dielectric and at least one gate conductor. As usedherein, a “gate dielectric” is a layer of an insulator between thesemiconductor device substrate of a planar device, or fin structure, andthe gate conductor. A “gate conductor” means a conductive structure ofthe gate structure on the gate dielectric. The field effect transistors(FETs) that are used with the methods and structures provided herein mayinclude planar field effect transistors, planar field effect transistorson bulk substrates, planar field effect transistors on SOI substrates,partially depicted field effect transistors, fully depleted field effecttransistors, Fin Field Effect Transistors (FinFETs), nanowire fieldeffect transistors, trigate field effect transistors, horizontalnanowire or nano-sheet semiconductor devices, or vertical nanowire ornanosheets semiconductor devices.

III-V compound semiconductors, such as gallium arsenic (GaAs), indiumgallium arsenic (InGaAs), indium arsenic (InAs) and indium antimonide(InSb), are semiconductors considered for use in n-type FET and p-typeFET devices for complementary metal oxide semiconductor (CMOS)applications. In some embodiments, the present disclosure provides gatestacks for III-V s emiconductor channel field effect transistor (FETs)with a high capacitance and low gate leakage current. It has beendetermined that the typically employed hafnium oxide (HfO₂)/aluminumoxide (Al₂O₃)/indium gallium arsenide (InGaAs) gate stack exhibitshigher gate leakage than what was previously understood.

In some embodiments, the methods disclosed herein provide an oxidizingtreatment that can be performed after the deposition, e.g., firstdeposition or only deposition, of the material layer for a high-k gatedielectric that has been formed on a III-V semiconductor substrate. Ithas been determined that the disclosed oxidizing treatment beneficiallyreduces gate leakage without adversely affecting, i.e., reducing, gatecapacitance. As will be described in greater detail below, the preferredoxidizing treatment employs ozone (O₃). In one embodiment, in which thegate stack composes hafnium oxide (HfO₂)/aluminum oxide (Al₂O₃)/InGaAs,the disclosed process sequence includes the deposition of an aluminumoxide layer (Al₂O₃) followed by the oxidizing treatment, e.g., ozone(O₃) treatment, wherein the oxidizing treatment is followed by thedeposition of hafnium oxide (HfO₂). In some embodiments, the oxidizingtreatment, e.g., ozone (O₃) treatment, dramatically reduce gate leakagewhile increasing gate capacitance. In some embodiments, the oxidizingtreatment increases gate capacitance and decreases gate leakage bymodifying, e.g., oxidizing, the III-V substrate surface at the channelregion, e.g., oxidizing the InGaAs channel region at the interface withthe gate dielectric. For example, an oxide may be formed between themetal oxide layer and the channel portion of the III-V substrate, whichis some examples includes gallium oxide (Ga_(x)O_(y)). The methods andstructures of this embodiment are now described with greater detailreferring to FIGS. 1-7.

FIG. 1 is a flow chart illustrating one embodiment of a gate firstmethod for forming a semiconductor device on a III-V semiconductorsubstrate, as depicted in FIGS. 2-7. In some embodiments, the method maybegin with forming a metal oxide material 5 on a III-V semiconductorsubstrate 1 at step 50. Referring to FIG. 2, the III-V semiconductorsubstrate is composed of a III-V semiconductor material. The term “III-Vsemiconductor material” denotes a semiconductor material that includesat least one element from Group IIIB of the Periodic Table of Elementsunder the Old International Union of Pure and Applied Chemistry (IUPAC)classification system, or Group 13 of the New International Union ofPure and Applied Chemistry classification system; and at least oneelement from Group VB of the Periodic Table of Elements, or Group 15 ofthe New International Union of Pure and Applied Chemistry classificationsystem. In some embodiments, the III-V semiconductor material thatprovides the III-V semiconductor substrate 1 may be selected from thegroup of gallium antimonide (GaSb), indium antimonide (InSb), indiumgallium antimonide (InGaSb), aluminum antimonide (AlSb), aluminumarsenide (AlAs), aluminum nitride (AlN), aluminum phosphide (AlP),gallium arsenide (GaAs), gallium phosphide (GaP), indium antimonide(InSb), indium arsenic (InAs), indium nitride (InN), indium phosphide(InP), aluminum gallium arsenide (AlGaAs), indium gallium phosphide(InGaP), aluminum indium arsenic (AlInAs), aluminum indium antimonide(AlInSb), gallium arsenide nitride (GaAsN), gallium arsenide antimonide(GaAsSb), aluminum gallium nitride (AlGaN), aluminum gallium phosphide(AlGaP), indium gallium nitride (InGaN), indium arsenide antimonide(InAsSb), indium gallium antimonide (InGaSb), aluminum gallium indiumphosphide (AlGaInP), aluminum gallium arsenide phosphide (AlGaAsP),indium gallium arsenide phosphide (InGaAsP), indium arsenide antimonidephosphide (InArSbP), aluminum indium arsenide phosphide (AlInAsP),aluminum gallium arsenide nitride (AlGaAsN), indium gallium arsenidenitride (InGaAsN), indium aluminum arsenide nitride (InAlAsN), galliumarsenide antimonide nitride (GaAsSbN), gallium indium nitride arsenidealuminum antimonide (GaInNAsSb), gallium indium arsenide antimonidephosphide (GaInAsSbP), and combinations thereof. In one example, theIII-V substrate 1 may be composed of aluminum gallium arsenide (AlGaAs)in a bulk semiconductor substrate configuration. Although FIGS. 2-7depict a planar semiconductor device formed on a bulk substrate, thepresent disclosure is not limited to only this example. For example, theIII-V semiconductor substrate 1 may be a semiconductor on insulator(SOI) substrate, e.g., silicon on insulator substrate, extremely thinsemiconductor on insulator (ETSOI) substrate, or the semiconductorsubstrate 1 may be fin type structures, such as a fin type structureemployed in Fin Field Effect Transistors (FinFETs).

FIG. 2 depicts one embodiment of forming a metal oxide material 50 on aIII-V semiconductor channel region, e.g., as provided by a III-Vsemiconductor substrate 1, or a germanium containing substrate. In theembodiment, the metal oxide material 50 may be composed of aluminumoxide (Al₂O₃). It is noted that aluminum oxide (Al₂O₃) is only oneexample of a metal oxide material 50 that can be used at this step ofthe present disclosure, and it is not intended that the metal oxidematerial 50 be limited to only this example. For example, the metaloxide material 50 may also be composed of zirconium oxide (ZrO₂),lanthanum oxide (La₂O₃) or combinations thereof including combinationswith aluminum oxide (Al₂O₃). The metal oxide material 50 may bedeposited using atomic layer deposition (ALD) or chemical vapordeposition (CVD). “Atomic layer deposition” (ALD) as used herein refersto a vapor deposition process in which numerous consecutive depositioncycles are conducted in a deposition chamber. Typically, during eachcycle a metal precursor is chemisorbed to the substrate surface, i.e.,surface of the low-k dielectric material 30; excess precursor is purgedout; a subsequent precursor and/or reaction gas is introduced to reactwith the chemisorbed layer; and excess reaction gas (if used) andby-products are removed.

Chemical vapor deposition (CVD) is a deposition process in which adeposited species is formed as a result of chemical reaction between atleast two gaseous reactants at greater than room temperature (25° C. to900° C.); wherein solid product of the reaction is deposited on thesurface on which a film, coating, or layer of the solid product is to beformed. Variations of CVD processes include, but not limited to,Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and PlasmaEnhanced CVD (PECVD), Metal-Organic CVD (MOCVD) and combinations thereofmay also be employed.

The thickness of the metal oxide material 5 may range from 1 Å to 10 Å.In some embodiments, the thickness of the metal oxide material 5 mayrange from 2 Å to 5 Å.

Following formation of the metal oxide material, the method may continueto step 52 of FIG. 1, which includes treating the metal oxide with anoxidation process 6, as depicted in FIG. 3. The term “oxidation process”denotes a process that introduces at least one oxygen containing elementor species that reacts with at least one element of a material to whichthe oxidation process is being applied, which results in the formationof an oxide. In some embodiments, treating of the metal oxide materialwith the oxidation process includes an ozone containing gas, and isconducted in a same deposition chamber that deposits said metal oxidelayer without an air break. For example, if the metal oxide material 5is deposited using an atomic layer deposition (ALD) apparatus, followingthe deposition of the metal oxide material 5, the atomic layerdeposition chamber is pumped down to remove any precursor gas that wasused to deposit the metal oxide material, the temperature of thedeposition chamber is adjusted for the oxidation process, and theprecursors for the oxidation process are pumped into the depositionchamber including the substrate including the metal oxide material 5without an air break between those steps. By “without an air break” itis meant that there is no disruption of the deposition chamber vacuumand/or atmosphere that would introduce air, i.e., the ambient atmospherethe deposition chamber, into the deposition chamber at which theoxidation process is being performed.

In some embodiments, the gas precursors for the oxidation process 6 mayinclude ozone (O₃) gas, H₂O gas, NO, N₂O, atomic oxygen gas or acombination thereof. Although the gas precursors are typicallyintroduced to the metal oxide material 5 following its depositionwithout air break, in some examples, the use of an air break has beencontemplated for using atmospheric air as the gas for providing theoxidation process 6. In other embodiments, the oxidation process 6 mayinclude a plasma. In some embodiments, the plasma that is employed forthe oxidation process may include at least one of O₂, H₂O, NO, N₂O andcombinations thereof.

In one embodiment, the oxidation process comprises a oxidation treatmenttemperature ranging from approximately 20° C. to 500° C. The oxidationprocess, i.e., application of the gas precursor and/or plasma, and theapplication of the oxidation treatment temperature may be maintainedwhile the metal oxide material 5 is present within the depositionchamber for a time period ranging from 1 second to 10 minutes. In oneembodiment, a different oxygen containing precursor is used in theoxidation process than the precursor used in the deposition process fordepositing the metal oxide material, wherein an exposure precursor timeduring the oxidation process is greater than an exposure precursor timeduring forming the metal oxide material.

In some embodiments, the oxidation process 6 forms an oxide region 5 acomposed of an element from the III-V substrate 1, e.g., gallium (Ga)from a III-V substrate 1 composed of InGaAs, that extends from the lowersurface of the metal oxide material 5, e.g., a metal oxide material 5provided by an Al₂O₃ layer. The concentration of the element from theIII-V substrate that is present in the oxide region 5 a may have ahigher concentration in the portion of the oxide region 5 a that isabutting, i.e., in direct contact with, the metal oxide material 5,e.g., Al₂O₃ layer, and the concentration of the element from the III-Vsubstrate, e.g., Gallium (Ga) that is present in the oxide region 5 adecreases as extending away from the interface with the metal oxidematerial, e.g., Al₂O₃ layer, into the substrate 1. The overall thicknessof the oxide region 5 a may range from 1 Å to 10 Å. In some embodiments,the overall thickness of the oxide region 5 a may range from 2 Å to 5 Å.It is noted that there may be some hafnium from the later formed hafniumcontaining dielectric 15 that diffuses to and alloys with the oxideregion 5 a, as well as metal from the metal oxide material 5 thatdiffuses to and alloys with the oxide region 5 a.

The oxidizing treatment 6, e.g., ozone (O₃) treatment, dramaticallyreduces gate leakage while increasing gate capacitance in the finaldevice structure including a gate stack of the metal oxide material 5and the oxide region 5 a.

Following the application of the oxidation process 6, the method maycontinue to step 53 of FIG. 1, which includes depositing of a hafniumcontaining oxide 15 on the metal oxide material 5 after the oxidationprocess, as depicted in FIG. 4. One example of a hafnium containingoxide 15 that is suitable for use with the present disclosure is hafniumoxide (HfO₂). It is noted that hafnium oxide (HfO₂) is not the onlymaterial that is suitable for the hafnium containing oxide 15. Examplesof such Hf-based dielectrics that are suitable for the hafniumcontaining oxide may include hafnium oxide (HfO₂), hafnium silicate(HfSiOx), Hf silicon oxynitride (HfSiON) or multilayers thereof. In someother examples, the hafnium containing oxide 15 may be substituted withanother high-k composition. The term “high-k” denotes a dielectricmaterial having a dielectric constant greater than silicon oxide (SiO₂)at room temperature (20° C. to 25° C.) and atmospheric pressure (1 atm).For example, a high-k material may have a dielectric constant greaterthan 4.0. In another example, the high-k material has a dielectricconstant greater than 7.0. Examples of high-k dielectrics that do notinclude hafnium are ZrO₂ or rare earth oxides, such as La₂O₃. MgO orMgNO can also be used. The at least one hafnium containing oxide 15 mayhave a thickness ranging from about 1.0 Å to about 50.0 Å. It is notedthat there may be some hafnium from the hafnium containing dielectric 15that diffuses to and alloys with the oxide region 5 a.

Referring to FIG. 1, the method may continue at step 53 with forming agate conductor 20 atop the hafnium containing oxide 15. The gateconductor 20 may include a doped semiconductor, e.g., n-type dopedpolysilicon, a metal or a metal nitride, and may be a single layerstructure or a multi-layer structure. For example, in some embodiment,composed of a metal nitride, such as titanium nitride (TiN). In someexamples, the gate conductor 20 may include an electrically conductivematerial layer in which work function adjustments are provided by a workfunction adjustable layer. For example, when the gate conductor 20includes TiN, stoichiometric tuning can be accomplished by adjusting thetitanium (Ti) to nitrogen (N) ratio during the physical vapor deposition(PVD) sputtering program for forming the material layer of the gateconductor 20. Although titanium nitride (TiN) is described above as anembodiment of a material suitable for the gate conductor with a workfunction adjustment, other metal nitrides may be suitable for use withthe present disclosure. For example, the metal layers for work functionadjustments may further comprise aluminum. In other examples, metal workfunction adjusting layers may include other metals from Groups IVB toVIB in the Periodic Table, including, e.g., tantalum nitride (TaN),niobium nitride (NbN), vanadium nitride (VN), tungsten nitride (WN), andthe like with a thickness of about 20 Angstroms to about 30 Angstroms.

The conductive electrode i.e., gate conductor 20, may be composed of anymetal containing material. For example, the gate conductor 20 may becomposed of tungsten (W) or a tungsten including alloy. In otherexamples, the gate conductor 20 is composed of aluminum (Al), copper(Cu), platinum (Pt), silver (Ag) or an alloy thereof including alloyswith tungsten (W).

The gate conductor 20 may be deposited using physical vapor deposition(PVD), such as plating, electroplating, electroless plating, sputteringand combinations thereof. In other embodiments, the gate conductor 20may be deposited using chemical vapor deposition (CVD), such as plasmaenhanced chemical vapor deposition (PECVD).

Referring to FIG. 1, the method may progress to step 54, which includespatterning the gate conductor 20, the hafnium containing oxide 15, andthe metal oxide material 5. FIG. 6 depicts one embodiment of patterninga gate structure 60. The patterned gate structures 60 are formedutilizing photolithography and etch process steps. Specifically, apattern is produced by applying a photoresist to the surface to beetched; exposing the photoresist to a pattern of radiation; and thendeveloping the pattern into the photoresist utilizing conventionalresist developer. Once the patterning of the photoresist is completed,the sections covered by the photoresist are protected while the exposedregions are removed using a selective etching process that removes theunprotected regions. As used herein, the term “selective” in referenceto a material removal process denotes that the rate of material removalfor a first material is greater than the rate of removal for at leastanother material of the structure to which the material removal processis being applied. The etch process for patterning the gate structure 60may include an anisotropic etch, such as reactive ion etching (RIE).

Referring to FIG. 6, the method may continue with forming a gatesidewall spacer 21 on each of the gate structure 50. The gate sidewallspacer 21 may be composed of oxide, i.e., SiO₂, but may also comprisenitride or oxynitride materials. The gate sidewall spacer 21 can beformed by deposition and etch processes.

Following formation of the gate sidewall spacer 21, source regions 25and drain regions 30 are formed on opposing sides of the channel region,as depicted in FIG. 7. The source regions 25 and drain regions 30 may beformed using ion implantation, in which an n-type or p-type dopant isimplanted into the III-V semiconductor substrate 1. In some embodiments,a n-type dopant in a type III-V semiconductor material, such as InGaAs,can be element from Group IIA or VIA of the Periodic Table of Elements).As used herein, “n-type” refers to the addition of impurities thatcontributes free electrons to an intrinsic semiconductor. As usedherein, “p-type” refers to the addition of impurities to an intrinsicsemiconductor that creates deficiencies of valence electrons.

Although not depicted in the supplied figures the source and drainregions 25, 30 may further include raised source and drain regions.Raised source and drain regions may include in-situ doped epitaxiallyformed semiconductor material that is formed on the upper surface of thesubstrate 1 in which the source and drain regions 25, 30 are present.

FIGS. 8 illustrates a comparison of the gate leakage performance offield effect transistors (FETs) having gate structures formed using theabove described oxidation process, e.g., step 51 of the method that hasbeen described above with reference to FIG. 1., in comparison to thegate leakage performance of FETs that have not been treated with theoxidation process of the present disclosure. Plot 61 illustrates thegate leakage measured from a gate structure including a TiN gateconductor, a 35 Å thick hafnium oxide (HfO₂) layer, and a 5 Å thickaluminum oxide (AlO) layer that has been treated with a oxidationprocess, as described with reference to step 51 of the method sequencedepicted in FIG. 1. Plot 62 illustrates the gate leakage measured from agate structure including a TiN gate conductor, a 30 Å thick hafniumoxide (HfO2) layer, and a 5 Å thick aluminum oxide (AlO) layer that hasbeen treated with a oxidation process, as described with reference tostep 51 of the method sequence depicted in FIG. 1. Plot 63 illustratesthe gate leakage measured from a gate structure including a TiN gateconductor, a 30 Å thick hafnium oxide (HfO₂) layer, and a 10 Å thickaluminum oxide (AlO) layer that has been treated with a oxidationprocess, as described with reference to step 51 of the method sequencedepicted in FIG. 1.

Plot 64 illustrates the gate leakage measured from a gate structureincluding a TiN gate conductor, a 30 Å thick hafnium oxide (HfO₂) layer,and a 10 Å thick aluminum oxide (AlO) layer that has not been treatedwith an oxidation process, as described with reference to step 51 of themethod sequence depicted in FIG. 1. Plot 65 illustrates the gate leakagemeasured from a gate structure including a TiN gate conductor, and a 35Å thick hafnium oxide (HfO₂) layer that has not been treated with aoxidation process, as described with reference to step 51 of the methodsequence depicted in FIG. 1. Plot 66 illustrates the gate leakagemeasured from a gate structure including a TiN gate conductor, a 25 Åthick hafnium oxide (HfO₂) layer that has not been treated with aoxidation process and a 3 Å aluminum oxide layer, in which a oxide layeris between the hafnium oxide (HfO₂) and the aluminum oxide layer,wherein the gate structure has not been treated with an oxidationprocess, as described with reference to step 51 of the method sequencedepicted in FIG. 1. Plot 67 illustrates the gate leakage measured from agate structure including a TiN gate conductor, a 35 Å thick hafniumoxide (HfO₂) layer that has not been treated with a oxidation processand a 5 Å aluminum oxide (Al₂O₃) layer, wherein the gate structure hasnot been treated with an oxidation process, as described with referenceto step 51 of the method sequence depicted in FIG. 1. Plot 68illustrates the gate leakage measured from a gate structure including aTiN gate conductor, a 30 Å thick hafnium oxide (HfO₂) layer that has notbeen treated with a oxidation process and a 5 Å aluminum oxide (Al₂O₃)layer, wherein the gate structure has not been treated with an oxidationprocess, as described with reference to step 51 of the method sequencedepicted in FIG. 1.

Comparison of the gate structures that have been treated with theoxidation process, as described with reference to FIGS. 1-7, i.e.,including step 51, to the gate structures that were identically formedwith the exception of not including the oxidation process of the presentdisclosure reveals that the disclosed oxidation process provides reducedgate leakage.

FIG. 9 is a plot of electron energy loss spectroscopy (EELS) of an oxideregion 5 a formed in accordance with the method described above withreference to FIGS. 1-8, in which an aluminum oxide (Al₂O₃) metal oxidelayer 5 is formed on an indium gallium arsenide (InGaAs) substrate 1 andtreated with the above described oxidation process 6 to form the oxideregion 5 a. The EELS plots illustrate that the method depicted in FIGS.1-7 form an oxide region 5 a composed of gallium (Ga) extending from thelower surface of the metal oxide layer 5, e.g., Al₂O₃ layer, having ahigher gallium concentration abutting the Al₂O₃ layer and a lowergallium (Ga) concentration extending away from the interface with theAl₂O₃ layer into the substrate. In some embodiments, the Ga/As and Ga/Inratios are higher at the Al₂O₃ interface than in the bulk substrateIn0.53Ga0.47As, and lower in a thin area away from that interface. Insome embodiments, there can be some intermixing occurring in the oxideregion 5 a with the metal oxide layer 5 and the overlying hafniumcontaining layer 15.

The method depicted in FIGS. 1-7 is a gate first process. The methoddescribed with reference to FIGS. 1-9 is equally applicable to a gatelast process that employs a sacrificial gate structure prior to formingthe source and drain regions, and then replaces the sacrificial gatestructure with a functional gate structure after forming the source anddrain regions. FIG. 10 is a flow chart illustrating one embodiment of agate last method for forming a semiconductor device on a III-Vsemiconductor substrate 1.

Referring to FIGS. 10 and 11, the method may begin with forming asacrificial gate structure 35 on a III-V semiconductor substrate 1, andforming source and drain regions 25, 30 on opposing sides of a channelregion of a semiconductor device, at step 56. The II-V semiconductorsubstrate 1 that is depicted in FIG. 11 has been described above withreference to FIG. 2. For example, the III-V semiconductor substrate 1may be composed of InGaAs. In some embodiments, the sacrificial gatestructures 35 that are depicted in FIG. 10 are formed of a semiconductormaterial, such as polysilicon. But, in other embodiments, thesacrificial gate structures 35 may be composed of a dielectric material.The replacement gate structures 60 may be formed using deposition,photolithography and etching processes. The sacrificial gate structures35 are formed to have a geometry that matches the geometry of the laterformed functional gate structures.

Sidewall spacer 21 are formed on sidewalls of the sacrificial gatestructure 35 similar to the sidewall spacer 21 that has been describedabove with reference to FIG. 7. The above description of the sidewallspacers 21 that are depicted in FIG. 7 is suitable for the descriptionof the sidewall spacer that is depicted in FIG. 11.

The source and drain regions 25, 30 may be formed using ionimplantation. Some examples of the processing and the composition of thesource and drain regions 25, 30 that are depicted in FIG. 11 is providedabove with reference to the source and drain regions 25, 30 that aredepicted in FIG. 7. For example, the source and drain regions 25, 30depicted in FIG. 11 may be formed using ion implantation of n-type orp-type dopants.

Referring to FIGS. 10 and 11, following formation of the source anddrain regions 25, 30, a dielectric layer 36 may be formed having anupper surface that is coplanar with the sacrificial gate structure 35 atstep 57. The dielectric layer 36 may be deposited using chemicalsolution deposition, spin on deposition, chemical vapor deposition or acombination thereof. The dielectric layer 36 may be selected from thegroup consisting of silicon containing materials such as SiO₂, Si₃N₄,SiO_(x)N_(y), SiC, SiCO, SiCOH, and SiCH compounds, the above-mentionedsilicon containing materials with some or all of the Si replaced by Ge,carbon doped oxides, inorganic oxides, inorganic polymers, hybridpolymers, organic polymers such as polyamides or SiLK™, other carboncontaining materials, organo-inorganic materials such as spin-on glassesand silsesquioxane-based materials, and diamond-like carbon (DLC), alsoknown as amorphous hydrogenated carbon, α-C:H). Additional choices forthe interlevel dielectric layer include any of the aforementionedmaterials in porous form, or in a form that changes during processing toor from being porous and/or permeable to being non-porous and/ornon-permeable. Following deposition, the dielectric layer 36 may beplanarized to provide an upper surface that is coplanar with an exposedupper surface of the sacrificial gate structures 35. In one example, theplanarization process is chemical mechanical planarization (CMP).

Referring to FIGS. 10 and 12, at step 58, the method may continue withremoving the sacrificial gate structure 35 to provide a gate opening 40to the channel region of the semiconductor device. The sacrificial gatestructures 35 may be removed using a selective etch process.

Referring to FIG. 10, the method may continue with forming a metal oxidematerial on the channel region of the III-V semiconductor substrate 1 atstep 59. FIG. 13 depicts one embodiment of forming a metal oxidematerial 5 on a III-V semiconductor channel region of the III-Vsemiconductor substrate 1. The metal oxide material 5 is formed withinthe gate opening 40, and is present on at least a base surface of thegate opening 40 that is provided by the upper surface of the channelportion of the III-V semiconductor substrate 1. In some embodiments,portions of the metal oxide material 5 may also be present on thesidewalls of the gate opening 40 provided by the gate sidewall spacers21. The metal oxide material 5 that is depicted in FIG. 13 is similar tothe metal oxide material 5 that is described above with reference toFIG. 2. Therefore, the above description of the metal oxide material 5that is depicted in FIG. 2 is suitable for the metal oxide material thatis depicted in FIG. 13. For example, the metal oxide material may becomposed of aluminum oxide (Al₂O₃).

Referring to FIG. 10, in a following process step, i.e., at step 60, themethod can include treating the metal oxide material 5 with an oxidationprocess 6. As depicted in FIG. 14, the oxidation process 6 is applied ina gate last process flow after the source and drain regions 25, 30 havebeen formed. The oxidation process 6 that is depicted in FIG. 14 issimilar to the oxidation process 6 that is described above withreference to FIG. 3. For example, the oxidation process 6 employed inthe process flow described with reference to FIGS. 10-16 may includeozone and forms an oxide region 5 a in the III-V substrate underlyingthe metal oxide layer 5. Therefore, the above description of theoxidation process 6 that is depicted in FIG. 3 is suitable for theoxidation process 6 that is depicted in FIG. 14. Additionally, the abovedescription of the oxide region 5 a that is depicted in FIG. 3 issuitable for the oxide region 5 a that is depicted in FIG. 14.

For example, the oxide region 5 a depicted in FIG. 14 may be composed ofan element from the III-V substrate 1, e.g., gallium (Ga) from a III-Vsubstrate 1 composed of InGaAs, that extends from the lower surface ofthe metal oxide material 5, e.g., a metal oxide material 5 provided byan Al₂O₃ layer. The concentration of the element from the III-Vsubstrate that is present in the oxide region 5 a may have a higherconcentration in the portion of the oxide region 5 a that is abutting,i.e., in direct contact with, the metal oxide material 5, e.g., Al₂O₃layer, and the concentration of the element from the III-V substrate,e.g., Gallium (Ga) that is present in the oxide region 5 a decreases asextending away from the interface with the metal oxide material, e.g.,Al₂O₃ layer, into the substrate 1. It is noted that there may be somehafnium from the later formed hafnium containing dielectric 15 thatdiffuses to and alloys with the oxide region 5 a, as well as metal fromthe metal oxide material 5 that diffuses to and alloys with the oxideregion 5 a. The oxidizing treatment 6, e.g., ozone (O₃) treatment,depicted in FIG. 14 can dramatically reduce gate leakage whileincreasing gate capacitance in the final device structure including agate stack of the metal oxide material 5 and the oxide region 5 a, asformed using the method described in FIGS. 10-16.

FIG. 15 depicts one embodiment of depositing of a hafnium containingoxide 15 on the metal oxide material 5 after the oxidation process 6 atstep 61 of the process flow depicted in FIG. 10. The hafnium containingoxide 15 that is depicted in FIG. 15 is similar to the hafniumcontaining oxide 15 that is described above with reference to FIG. 3.Therefore, the above description of the hafnium containing oxide 15 thatis depicted in FIG. 3 is suitable for the hafnium containing oxide 15that is depicted in FIG. 15. For example, the hafnium containing oxide15 may be composed of hafnium oxide (HfO₂). In some embodiments, thehafnium containing oxide material 15 is formed within the gate opening40, and is present on the metal oxide material 5 on at least a basesurface of the gate opening 40 that is provided by the upper surface ofthe channel portion of the III-V semiconductor substrate 1. The hafniumcontaining oxide material may also be present on the sidewalls of thegate opening 40, i.e., be formed on the portions of the metal oxidematerial 5 that are present on the sidewalls of the gate opening 40.

Referring to FIG. 10, in one embodiment, the method may continue withstep 62 with forming a gate conductor 20 on the hafnium containing oxide15. FIG. 16 depicts one embodiment of forming gate conductor 20 on thehafnium containing oxide 5. In some embodiments the gate conductor 20may fill the gate opening 40. For example, the gate conductor 20 may beoverfilled, and then planarized, e.g., by chemical mechanicalplanarization (CMP), to provide that an upper surface of the gateconductor is coplanar with an upper surface of the dielectric layer 36.The gate conductor 20 that is depicted in FIG. 16 is similar to the gateconductor 20 that is described above with reference to FIG. 6.Therefore, the above description of the gate conductor 20 that isdepicted in FIG. 6 is suitable for the gate conductor 20 that isdepicted in FIG. 16.

FIG. 17 illustrates another embodiment of a gate first method of thepresent disclosure that forms a semiconductor device on a germaniumcontaining substrate, e.g., silicon germanium substrate. The term“germanium containing” denotes that the substrate includes at least 10at. % germanium. For example, the germanium containing substrate mayinclude be composed of germanium (Ge) or silicon germanium (Ge). Agermanium substrate may be substantially 100 at. % germanium (Ge), e.g.,greater than 95 at. % germanium (Ge). In some instances, a substantially100 at. % germanium substrate may be 99.99 at. % germanium or greater.Examples of silicon germanium (SiGe) suitable for the germaniumcontaining substrate include Si_(0.25) Ge_(0.75), Si_(0.5) Ge_(0.5),Si_(0.75) Ge_(0.25) and combinations thereof.

SiGe channels are an alternative channel material to Si channel due totheir comparatively higher electron and hole mobility, but it has beendetermined that the formation of high quality interfacial layer (IL) ischallenging on substrates that are composed of silicon germanium (SiGe).It has been further determined that previous attempts at forminginterfacial layers on SiGe substrates, such as high pressure oxidation(HPO), are insufficient in view of aggressive device scaling, becausethe growth GeO₂ using these prior methods is too thick and equivalentoxide thickness (EOT) scaling is hampered. “Equivalent oxide thickness(EOT)” is a distance, usually given in nanometers (nm), which indicateshow thick a silicon oxide film would need to be to produce the sameeffect as the high-k material being used. Additionally, post plasmaoxidation (PPO) is not suitable for 3-D structures, such as FinFETs orNanowire FETs, due to directional nature of plasma process.

In some embodiments, the methods and structures disclosed herein canprovide for EOT scaling with low gate leakagecurrent/low-interface-state-density (Dit) on silicon germanium (SiGe)channels. In some examples, the channel of the semiconductor devicesdisclosed herein may include silicon germanium (SiGe) with varyinggermanium (Ge) percentage, e.g., germanium (Ge) percentage varying from20% to 100%. In some examples, the method disclosed herein, e.g., asillustrated in FIG. 17, can provide an interfacial layer that includesgermanium and oxygen in combination with silicon and nitrogen. Theinterfacial layer may be underling a high-k gate dielectric, such ashafnium aluminium oxide (HfAlO).

In some embodiments, the method for forming an interfacial layer on asilicon germanium channel region includes a process sequence in anatomic layer deposition (ALD) tool, which includes the steps of: (1) ALDAl₂O₃ (Al precursor+H₂O) (2) O₃ pulse, and (3) ALD HfO₂ (Hfprecursor+H₂O). In some embodiments, the method may include an optionalpost high-k deposition nitridation treatment that could include a NH₃thermal anneal, N₂ plasma or NH₃ plasma. The methods and gate structurescan be implemented in a gate stack that can be applicable to both nFETand pFET devices, and is applicable to both planar and 3D structures,e.g. FinFET, and Nanowire FETs.

The methods and structures for forming an interfacial layer on a channelregion composed of silicon germanium is now described in greater detailwith reference to FIGS. 17-19.

FIG. 17 is a flow chart illustrating one embodiment of a gate firstmethod for forming a semiconductor device on a germanium containingsubstrate. The method may begin with forming a metal oxide material on aSiGe semiconductor channel region at step 50 a. The germanium channelregion may be provided by a semiconductor substrate composed ofgermanium (Ge), single crystal germanium (Ge), polycrystalline germanium(Ge), silicon germanium (SiGe), silicon germanium doped with carbon(SiGe:C), and combinations thereof. In one example, the germaniumchannel region is provided by single crystalline silicon germanium(c-SiGe).

It is noted that step 50 a is similar to step 50 of the method depictedin FIG. 1 with the exception that the substrate is composed of agermanium containing semiconductor, as opposed to a type III-Vsemiconductor material. Therefore, the above description of the metaloxide material 5, as depicted in FIG. 2, for the method described withreference to FIGS. 1-9 is suitable for describing the metal oxidematerial for the method illustrated by FIG. 17. For example, the metaloxide material 5 deposited on the germanium containing substrate may becomposed of zirconium oxide (ZrO₂), aluminum oxide (Al₂O₃), lanthanumoxide (La₂O₃) or combinations thereof. Although atomic layer deposition(ALD) can be utilized to deposit the metal oxide material 5, the presentdisclosure is not limited to only this example, as the metal oxidematerial 5 may also be deposition on a germanium containing substrateusing chemical vapor deposition (CVD). In one example, the metal oxidematerial 5 is an aluminum oxide (Al₂O₃) deposited to a thickness of 5angstroms.

In some embodiments, when using atomic layer deposition (ALD), the metaloxide material 5 may be formed from a metal containing precursor and awater precursor. For example, when the metal oxide material is composedof aluminum oxide, the metal containing precursor may include aluminum(Al).

In a following process step 51 a, the method may continue with treatingthe metal oxide material with an oxidation process. It is noted thatstep 51 a is similar to step 51 of the method depicted in FIG. 1 withthe exception that the substrate is composed of a germanium containingsemiconductor, as opposed to a type III-V semiconductor material.Therefore, the above description of the oxidation process 6, as depictedin FIG. 2, for the method described with reference to FIGS. 1-9 issuitable for describing the metal oxide material for the methodillustrated by FIG. 17. In some embodiments, the oxidation process mayinclude an ozone (O₃) treatment at a temperature ranging from 200° C. to400° C. for a time period of 30 seconds to 90 seconds. In one example,the oxidation process includes ozone gas applied to the metal oxidematerial 5 at a temperature of 300° C. for a time period of 60 seconds.

In some embodiments, the ozone treatment may be applied to the metaloxide material 5 is the same deposition chamber that the metal oxidematerial 5 was formed in without an air break. It is noted that ozone(O₃) is only one example of a material that is suitable for theoxidation process. The oxidation process may also include H₂O gas, NO,N₂O, atomic oxygen gas, air or a combination thereof or the oxidationprocess comprises a plasma comprising including at least one of O₂, H₂O,NO, N₂O and combinations thereof. In other embodiments, the ozonetreatment may be applied to the metal oxide material 5 after an airbreak.

In some embodiments, the in situ ozone (O₃) exposure at a temperature of300° C., and a time period of 60 seconds produces a high quality oxideregion 5 a underlying the metal oxide material 5 at the interface of themetal oxide material, e.g., aluminum oxide (Al₂O₃) and the germaniumcontaining substrate, e.g., silicon germanium (SiGe) substrate. Forexample, the oxide region 5 a may be composed of germanium oxide (GeO₂).The thickness of the oxide region 5 a may range from 1 Å to 5 Å, and insome instances may be equal to 2 Å. The oxide region 5 a may be composedof 0% to 33% silicon, 33% to 0% germanium (Ge), 60% to 70% oxygen (O).The ratio of silicon and germanium is determined by the composition ofthe SiGe channel. In the case of Ge and SiGe with Ge fraction greaterthan 85%, the oxide region 5 a predominantly consists from GeO₂. As willdescribed further below, an optional nitridation treatment may befurther applied to the structure, which could incorporate nitrogen intothe oxide region 5 a that may range from 1% to 30% in concentration,substituting oxygen atoms. In some embodiments, the oxide region 5 a,which may also be referred to as an interfacial layer (IL), may be(Si)GeO(N).

FIG. 18 depicts one embodiment of a plot of Z-contrast scanningtransmission electron microscope (Z-contrast STEM) of an oxide region 5a produced by a process sequence that included depositing an aluminumoxide layer having a thickness of 5 Å on a crystalline silicon germaniumsubstrate by ALD, an ozone (O₃) treatment for 60 seconds and a hafniumoxide layer being deposited after the ozone treatment having a thicknessof 20 Å. This data is plotted by reference line 77. The plot identifiedby reference line 76 is a similarly prepared structure but does notinclude the ozone treatment. Comparison of the plot identified byreference number 76 to the plot line identified by reference line 77indicates the presence of an oxide region 5 a having a thickness of 2 Å.

FIG. 19 is an electron energy loss spectroscopy (EELS) plot of thecomposition of an oxide region 5 a that is formed using the methoddescribed with reference to FIG. 17. The plot identified by referencenumber 78 a is for germanium (Ge), the plot identified by referencenumber 79 a is for aluminum (Al), the plot identified by referencenumber 80 a is for nitrogen, the plot identified by reference number 81a is for oxygen, the plot identified by reference number 82 a is fortitanium, and the plot identified by reference number 83 a is forhafnium. FIG. 20 is an electron energy loss spectroscopy (EELS) plot ofa comparative composition of an oxide region 5 a that is formed using amethod similar to the method described with reference to FIG. 17, butthe method for forming the comparative composition does not include anoxidation step. The plot identified by reference number 78 b is forgermanium (Ge), the plot identified by reference number 79 b is foraluminum (Al), the plot identified by reference number 80 b is fornitrogen, the plot identified by reference number 81 b is for oxygen,the plot identified by reference number 82 b is for titanium, and theplot identified by reference number 83 b is for hafnium. Comparison ofthe plots depicted in FIGS. 19 and 20 illustrate intermixing of hafniumand aluminum within the oxide region 5 a formed using the methoddescribed with reference to FIG. 17.

Referring to FIG. 17, the method may continue with forming a hafniumcontaining oxide 15 on the metal oxide material 5 after the oxidationprocess at step 52 a. It is noted that step 52 a is similar to step 52of the method depicted in FIG. 1 with the exception that the substrateis composed of a germanium containing semiconductor, as opposed to atype III-V semiconductor material. Therefore, the above description ofthe hafnium containing oxide, as depicted in FIG. 2, for the methoddescribed with reference to FIGS. 1-9 is suitable for describing thehafnium containing oxide 15 for the method illustrated by FIG. 17. Forexample, the hafnium containing oxide 15 may be hafnium oxide (HfO₂),which may be deposited after the oxidation process 6 by atomic layerdeposition with, or without, an air break between the oxidation process6 and the formation of the hafnium containing oxide 15. In oneembodiment, the process flow to this stage of the method may includedepositing an aluminum oxide layer (Al₂O₃), i.e., metal oxide materialwith a thickness of 5 Å; treatment with an oxidation process includingozone gas for 60 seconds, and depositing a hafnium oxide layer having athickness of 10 Å, wherein the process is conducted in the depositionchamber of an atomic layer deposition (ALD) apparatus without an airbreak.

Referring to FIG. 17, the method may continue with forming a gateconductor atop the hafnium containing oxide at step 53 a. It is notedthat step 53 a is similar to step 53 of the method depicted in FIG. 1with the exception that the substrate is composed of a germaniumcontaining semiconductor, as opposed to a type III-V semiconductormaterial. Therefore, the above description of the gate conductor 20, asdepicted in FIG. 2, for the method described with reference to FIGS. 1-9is suitable for describing the gate conductor for the method illustratedby FIG. 17.

At step 54 a of the process flow depicted in FIG. 17, the method maycontinue with patterning the gate conductor, hafnium containing oxideand the metal oxide material that was oxidized. This sequence of stepshas been described above with reference to step 54 of the methoddescribed with reference to FIGS. 1-9. Referring to FIG. 17, the methodmay continue with forming source and drain regions at step 55 a. Thesource and drain regions may be formed by ion implanting n-type orp-type dopants into the germanium containing substrate on opposing sidesof the channel. Because, germanium containing materials, such as silicongermanium, are type IV semiconductors, examples of n-type dopants, i.e.,impurities, include but are not limited to, antimony, arsenic andphosphorous. Because, germanium containing materials, such as silicongermanium, are type IV semiconductors, an example of a p-type dopants,i.e., impurities, includes, but is not limited to boron.

FIG. 21 is a plot illustrating the electrical impact of the oxidationtreatment applied to a bilayer of aluminum oxide and hafnium oxide thatis formed on a germanium containing substrate, in accordance with themethod described with reference to FIG. 17. The gate structuresproviding the electrical performance depicted in FIG. 18 included ametal oxide material provided by aluminum oxide (Al₂O₃), and a hafniumcontaining dielectric provided by hafnium oxide (HfO₂). The plotidentified by reference number 84 was from a gate stack including a 5 Åaluminum oxide layer (Al₂O₃) present on a substrate composed of 31%germanium (Ge), which was treated with an ozone (O₃) gas treatment, anda hafnium oxide (HfO₂) layer having a thickness of 20 Å that is presenton the aluminum oxide layer. The plot identified by reference number 85was from a gate stack including a 5 Å aluminum oxide layer (Al₂O₃)present on a substrate composed of 52% germanium (Ge), which was nottreated with an ozone (O₃) gas treatment, and a hafnium oxide (HfO₂)layer having a thickness of 20 Å that is present on the aluminum oxidelayer. The plot identified by reference number 86 was from a gate stackincluding a 5 Å aluminum oxide layer (Al₂O₃) present on a substratecomposed of 52% germanium (Ge), which was treated with an ozone (O₃) gastreatment, and a hafnium oxide (HfO₂) layer having a thickness of 20 Åthat is present on the aluminum oxide layer. The plot identified byreference number 87 was from a gate stack including a 5 Å aluminum oxidelayer (Al₂O₃) present on a substrate composed of 95% germanium (Ge),which was not treated with an ozone (O₃) gas treatment, and a hafniumoxide (HfO₂) layer having a thickness of 20 Å that is present on thealuminum oxide layer. The plot identified by reference number 88 wasfrom a gate stack including a 5 Å aluminum oxide layer (Al₂O₃) presenton a substrate composed of 95% germanium (Ge), which was treated with anozone (O₃) gas treatment, and a hafnium oxide (HfO₂) layer having athickness of 20 Å that is present on the aluminum oxide layer.

FIG. 21 illustrates an increase of Toxgl by 7 Å, which is equivalent to1000× gate leakage current density (J), with much smaller increase inCET and 2X interface state density (D_(it)) reduction for a materialstack including the oxidation process as described with reference toFig. 17, in comparison to a similar material stack that was not treatedwith the oxidation process described in FIG. 17.

In some embodiments, the method depicted in FIG. 17 may include anoptional nitridation step that is applied after the formation of thehafnium containing oxide. For example, the nitridation step may includea thermal anneal in a nitrogen containing gas atmosphere, e.g., NH₃thermal anneal. The anneal temperature may range from 600° C. to 700° C.In another example, the nitridation step may include a plasma treatment,in which the plasma may include N₂ and/or NH₃ plasma. The nitridationprocess may incorporate nitrogen (N) into the oxide region 5 a, whichmay also be referred to as an interfacial layer (IL). The incorporationof nitrogen into the oxide region produced using the process sequenceillustrated by FIG. 17 may provide further capacitance equivalentthickness (CET) scaling, as depicted in FIG. 22. FIG. 22 is a plotillustrating the electrical impact of the optional nitridation treatmentapplied to a bilayer of aluminum oxide and hafnium oxide.

The process flow described in FIG. 17 is a gate first process flow. Thepresent disclosure is not limited to only this process flow, as theoxidation step described in FIG. 17 is equally applicable to a gate lastprocess flow. FIG. 23 is a flow chart illustrating one embodiment of agate last method for forming a semiconductor device on a germaniumcontaining semiconductor substrate, in accordance with one embodiment ofthe present disclosure.

Referring to FIG. 23, the method may begin with forming a sacrificialgate structure on a germanium containing substrate, and forming sourceand drain regions on opposing sides of a channel region of asemiconductor device, at step 56 a. It is noted that step 56 a issimilar to step 56 of the method depicted in FIG. 10 with the exceptionthat the substrate is composed of a germanium containing semiconductor,as opposed to a type III-V semiconductor material, and the source anddrain regions are composed of dopants for type IV semiconductors.Therefore, the above description of forming a sacrificial gate structure35 and source and drain regions 25, 30, as depicted in FIG. 11, for themethod described with reference to FIGS. 10-16 is suitable fordescribing the formation of the sacrificial gate structure 35 and sourceand drain regions 25, 30 for the method illustrated by FIG. 23. Then-type and p-type dopants for the source and drain regions being formedin the germanium containing substrate 1 have been described withreference to FIG. 17.

Referring to FIG. 23, the method may continue with step 57 a, whichincludes forming a dielectric layer overlying the source and drainregions and having an upper surface coplanar with the upper surface ofthe sacrificial gate structure. Step 56 a is similar to step 56 of themethod depicted in FIG. 10 with the exception that the substrate iscomposed of a germanium containing semiconductor, as opposed to a typeIII-V semiconductor material. Therefore, the above description of theinterlevel dielectric 36, as depicted in FIG. 11, for the methoddescribed with reference to FIGS. 10-16 is suitable for describing theformation of the dielectric layer for the method illustrated by FIG. 23.

Step 58 a of the method sequence in FIG. 23 includes removing thesacrificial gate structure to form a gate opening to the channel.Removing the sacrificial gate structure has been described above in step58 of FIG. 10, as depicted in FIG. 12.

Referring to FIG. 23, in a following step, a metal oxide material isformed in the gate opening at step 59 a. Step 59 a is similar to step 59of the method depicted in FIG. 10 with the exception that the substrateis composed of a germanium containing semiconductor, as opposed to atype III-V semiconductor material. Therefore, the above description ofthe metal oxide material 5, as depicted in FIG. 13, for the methoddescribed with reference to FIGS. 10-16 is suitable for describing theformation of the metal oxide material for the method illustrated by FIG.23.

The method illustrated in FIG. 23 may continue with step 60 a, whichincludes treating the metal oxide material with an oxidation process.Step 60 a is similar to step 60 of the method depicted in FIG. 10 withthe exception that the substrate is composed of a germanium containingsemiconductor, as opposed to a type III-V semiconductor material.Therefore, the above description of the oxidation process 6, as depictedin FIG. 14, for the method described with reference to FIGS. 10-16 issuitable for describing the oxidation process for the method illustratedby FIG. 23. Further details of the oxidation process specific to formingdevices on germanium containing substrates may also be found abovereferring to step 51 a of the process flow illustrated in FIG. 17.

The oxidation process of step 51 a forms an oxide region, e.g.,germanium containing oxide, underlying the metal oxide material at aninterface with the metal oxide material and the germanium containingsubstrate. Further details regarding the oxide region are provided abovewith reference to step 51 a of FIG. 17. The impact of the oxidationprocess, e.g., electrical impact, is described above with reference toFIGS. 18-21.

Referring to FIG. 23, the method may continue with step 61 a, whichincludes treating forming the hafnium containing oxide on the metaloxide material. Step 61 a is similar to step 61 of the method depictedin FIG. 10 with the exception that the substrate is composed of agermanium containing semiconductor, as opposed to a type III-Vsemiconductor material. Therefore, the above description of the hafniumcontaining oxide 15, as depicted in FIG. 15, for the method describedwith reference to FIGS. 10-16 is suitable for describing the hafniumcontaining oxide for the method illustrated by FIG. 23. Further detailsof the hafnium containing oxide specific to forming devices on germaniumcontaining substrates may also be found above referring to step 52 a ofthe process flow illustrated in FIG. 17.

Referring to FIG. 23, in a following process, a gate conductor is formedatop the hafnium containing oxide at step 62 a. Step 62 a is similar tostep 62 of the method depicted in FIG. 10 with the exception that thesubstrate is composed of a germanium containing semiconductor, asopposed to a type III-V semiconductor material. Therefore, the abovedescription of the gate conductor 20, as depicted in FIG. 16, for themethod described with reference to FIGS. 10-16 is suitable fordescribing the gate conductor for the method illustrated by FIG. 23.Further details for the gate conductor 20 specific to forming devices ongermanium containing substrates may also be found above referring tostep 53 a of the process flow illustrated in FIG. 17.

It is noted that the process sequence illustrated in FIG. 23 may furtherinclude an optional nitridation step that is conducted after forming thehafnium containing oxide. The optional nitridation step is describedabove with reference to FIG. 17 and FIG. 22.

Although the structures depicted in the supplied drawings are planardevices, the present disclosure is not limited to only this example. Forexample, the methods disclosed herein may be suitable for forming gatestructures to FinFET devices, as depicted in FIGS. 24a and 24 b. FinFETdevices are field effect transistors in which the channel is present ina fin structure la. As used herein, a “fin structure” refers to asemiconductor material, which is employed as the body of a semiconductordevice, in which the gate structure is positioned around the finstructure such that charge flows down the channel on the two sidewallsof the fin structure la and optionally along the top surface of the finstructure la. In some embodiments, a fin structure may have a heightranging from 5 nm to 200 nm. In another embodiment, the fin structuremay have a height ranging from 10 nm to 100 nm. In some embodiments, thefin structures may have a width of less than 20 nm. In anotherembodiment, each of the fin structures has a width ranging from 3 nm to8 nm. The methods described with reference to FIGS. 1 and 10 may employa fin structure la that is composed of a type III-V semiconductormaterial. The methods described with reference to FIGS. 17 and 23 mayemploy a fin structure la that is composed of a germanium containingmaterial. The fin structure la may be present atop a supportingsubstrate lb, which may be a dielectric material. The metal oxidematerial 5, oxide region 5 a, the hafnium containing oxide layer 15, thegate conductor 20 and the source and drain regions 25, 30 that aredepicted in FIGS. 24a and 24b have been described above with referenceto FIGS. 1-23.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

1. A semiconductor device comprising: a channel region of a substratecomprising a germanium containing material; a gate structure comprisingan interface dielectric material comprising germanium, oxygen andnitrogen that is directly on the substrate, a high-k dielectric layercomprising hafnium, aluminum and oxygen on the interface dielectricmaterial, and a gate conductor present atop the high-k dielectric layer;and a source region and drain region on opposing sides of the channelregion.
 2. The semiconductor device of claim 1, wherein the interfacedielectric material is aluminum oxide, and a gallium enriched InGaAslayer is present adjacent to the high-k dielectric layer.
 3. Thesemiconductor device of claim 2, wherein a gallium concentration in theInGaAs layer decreases as the distance within the InGaAs layer increasesfrom the high-k dielectric layer.
 4. The semiconductor device of claim1, wherein the source and drain regions are present within thesubstrate.
 5. The semiconductor device of claim 4, wherein the sourceand drain regions are doped with an n-type dopant selected from thegroup consisting of antimony, arsenic and phosphorous.
 6. Thesemiconductor device of claim 4, wherein the source and drain regionsare doped with a p-type dopant of boron.
 7. The semiconductor device ofclaim 1, wherein interface dielectric material comprises (Si)GeO(N). 8.The semiconductor device of claim 1, wherein germanium containingmaterial is germanium, silicon germanium or a combination thereof.
 9. Asemiconductor device comprising: a channel region of a substratecomprising a III-V material; a gate structure comprising an interfacedielectric material comprising germanium, oxygen and nitrogen that isdirectly on the substrate, a high-k dielectric layer comprising hafnium,aluminum and oxygen on the interface dielectric material, and a gateconductor present atop the high-k dielectric layer; and a source regionand drain region on opposing sides of the channel region.
 10. Thesemiconductor device of claim 9, wherein the III-V semiconductor channelregion comprises a semiconductor material selected from the groupconsisting of gallium arsenide (GaAs), indium gallium arsenide (InGaAs),indium arsenide (InAs), indium phosphide (InP), gallium antimonide(GaSb), indium antimonide (InSb), indium gallium antimonide (InGaSb),and combinations thereof.
 11. The semiconductor device of claim 9,wherein the interface dielectric material is aluminum oxide, and agallium enriched InGaAs layer is present adjacent to the high-kdielectric layer.
 12. The semiconductor device of claim 11, wherein agallium concentration in the InGaAs layer decreases as the distancewithin the InGaAs layer increases from the high-k dielectric layer. 13.The semiconductor device of claim 9, wherein the source and drainregions are present within the substrate.
 14. The semiconductor deviceof claim 13, wherein the source and drain regions are doped with ann-type dopant selected from the group consisting of antimony, arsenicand phosphorous.
 15. The semiconductor device of claim 13, wherein thesource and drain regions are doped with a p-type dopant of boron. 16.The semiconductor device of claim 9, wherein interface dielectricmaterial comprises (Si)GeO(N).
 17. A gate material stack comprising: agate structure present on a germanium containing channel or III-Vsemiconductor channel, the gate structure comprising an interfacedielectric material comprising germanium, oxygen and nitrogen that isdirectly on the substrate, a high-k dielectric layer comprising hafnium,aluminum and oxygen on the interface dielectric material, and a gateconductor present atop the high-k dielectric layer.
 18. The gatematerial stack of claim 17, wherein the interface dielectric material isaluminum oxide, and a gallium enriched InGaAs layer is present adjacentto the high-k dielectric layer.
 19. The gate material stack of claim 17,wherein a gallium concentration in the InGaAs layer decreases as thedistance within the InGaAs layer increases from the high-k dielectriclayer.
 20. The gate material stack of claim 17, wherein interfacedielectric material comprises (Si)GeO(N).